01 / DEVICE STATE
Configure the real stack
Set absorber thickness, optical response, base doping, carrier lifetime, junction recombination, contact resistance, and operating conditions as explicit, auditable inputs.
FluxMateria Materials · Flagship
Solar devices,calculated from the stack.
Solar Device Studio carries FluxMateria from material properties into device performance: optical response, carrier collection, recombination, junction behavior, contacts, and the final J-V outputs engineers use to make decisions. The first qualified scope is conventional crystalline-silicon Al-BSF — with all four terminal accuracy gates passed.
Crystalline-Si Al-BSF
4 / 4 accuracy gates passed
No fitted correction factors
External lab qualification pending
Si Al-BSF device state
Qualified scope
Optical boundary
Measured spectral response
photons
Emitter + junction
Carrier separation and recombination
charge
Crystalline-Si absorber
Finite-thickness generation, transport, and collection
current
Al back-surface field
Rear-boundary response envelope
return
Terminal contacts
Series loss and delivered power
output
Jsc
current density
Voc
open-circuit voltage
FF
fill factor
PCE
efficiency
Internal qualification passed
384-device evidence panel, one production lineage
Independent published-profile check passed
Same-device Al-BSF record, all four gates
External laboratory qualification pending
Instrument-native, multi-lot campaign is the next gate
The platform leap
Materials physics that reaches the terminals.
Most materials platforms stop at a property table: band gap, mobility, conductivity.
FluxMateria composes those material states into a working device calculation.
Solar Device Studio follows energy from the incoming spectrum through the silicon stack and
returns the quantities a photovoltaic engineer actually needs: Jsc, Voc, fill factor, efficiency,
sensitivity, and a traceable validation receipt. This is what it means for one physics platform
to move from matter to technology.
What Solar Device Studio does now
A complete parameterized device loop for the qualified crystalline-Si Al-BSF scope.
02 / OPTICS
Resolve spectral generation
Carry the incident spectrum through measured front-surface response and finite silicon absorption instead of collapsing the device into a single broadband loss factor.
03 / TRANSPORT
Calculate collection through the wafer
Compose finite-thickness carrier transport with lifetime and doping to determine how much generated charge reaches the junction under retained rear-boundary limits.
04 / TERMINALS
Predict the full J-V outcome
Return Jsc, Voc, fill factor, and PCE from one internally consistent device state, with junction and contact losses carried into the terminal response.
05 / ROBUSTNESS
Stress the uncertain boundaries
Propagate optical and rear-boundary uncertainty through the final device metrics. A result passes only when the complete retained envelope remains inside the fixed gates.
06 / EVIDENCE
Produce audit-ready receipts
Preserve source lineage, input ownership, hashes, limitations, accuracy gates, and regression status so design claims remain reproducible and reviewable.
A device-design loop, not a lookup
From a measurable silicon state to a decision-ready terminal prediction.
1
Define the architecture
Choose the qualified p-type crystalline-Si full-area Al-BSF scope and set the physical geometry.
2
Load device-state inputs
Bring optical response, doping, lifetime, junction quality, and contact resistance with provenance.
3
Compose the physics
Resolve spectral generation, transport, recombination, and collection through the finite device.
4
Calculate J-V
Generate Jsc, Voc, fill factor, efficiency, and the retained boundary envelope.
5
Test the design
Apply fixed accuracy and robustness gates without selecting the boundary that looks best.
6
Hand off the evidence
Export a reproducible design and validation packet for engineering or laboratory review.
The current evidence
Bold claims, fixed gates, visible limitations.
0.671
Jsc error · mA/cm²
Goal ≤ 2.0 · PASS
0.0118
Voc error · V
Goal ≤ 0.025 · PASS
0.0162
Fill-factor error
Goal ≤ 0.035 · PASS
0.278
PCE error · percentage points
Goal ≤ 2.0 · PASS
Evidence scope: these headline values are worst-retained absolute errors on one
independent same-device published-profile Al-BSF check (n = 1), evaluated across the retained
rear-boundary envelope. They are positive independent transfer evidence, not an external certification.
| Terminal metric | Fixed goal | Internal qualification MAE | Independent check | Status |
|---|---|---|---|---|
| Jsc | ≤ 2.0 mA/cm² | 0.979 mA/cm² | 0.671 mA/cm² | PASS |
| Voc | ≤ 0.025 V | 0.00482 V | 0.0118 V | PASS |
| Fill factor | ≤ 0.035 | 0.00236 | 0.0162 | PASS |
| PCE | ≤ 2.0 pp | 0.420 pp | 0.278 pp | PASS |
Internal scope: the internal parameterized qualification uses a 384-device panel from
one production lineage. The independent check adds a separate same-device Al-BSF source with a
91-point published reflectance profile. Focused solar regressions pass 81 / 81 executed tests.
Decision speed
From a published cell to a design decision in 7.47 seconds.
7.47 s
Measured local runtime for the complete HBC case: baseline replay, published roadmap, 75-µm candidate, resistivity endpoints, gates, and evidence receipt.
The important comparison is not that every conventional device solve is slow—many are fast after setup. It is that FluxMateria turns a declared physical device state into a complete, auditable design comparison in one run. DFT remains invaluable upstream, but it cannot directly simulate an operating commercial-area cell atom by atom and return Jsc, Voc, fill factor, and PCE.
FluxMateria Solar Device Studio
Whole declared scenario · seconds
7.47 seconds in this case. One run compares the known cell, the published improvement roadmap, the thin-wafer candidate, and robustness endpoints, then emits the decision gates and evidence packet.
PV device simulation / TCAD
Powerful and often fast—after assembly
Conventional photovoltaic workflows combine optical and electrical solvers with explicit material, interface, geometry, and operating inputs. They are essential engineering tools, but runtime alone does not include parameter acquisition, model assembly, cross-solver handoff, or experimental qualification.
Density functional theory
DFT is not a whole-device alternative
Standard Kohn–Sham DFT has steep system-size scaling and is normally used for atomistic cells, defects, and interfaces. Even specialized linear-scaling work reaches thousands of atoms—not a 274.3-cm², 175-µm operating device. A direct full-cell DFT runtime is therefore not merely long; it is outside practical computational reach.
Comparison boundary: this is a workflow-and-scope comparison, not a claim that every individual TCAD solve is slower. Published context:
multiscale PV simulation joins specialized optical and electrical solvers;
conventional Kohn–Sham DFT has cubic-scaling cost and generally targets hundreds of atoms.
For scale, the early Materials Project DFT corpus used more than
15 million CPU-hours—a campaign-scale figure, not a per-device estimate.
The 7.47-second runtime is preserved in the downloadable case receipt and begins after source inputs and reusable module evidence are prepared; it does not include literature discovery, foundational module development, or fabrication.
Where the modeled gain came from
A cumulative PCE waterfall separates the published roadmap from the additional 75-µm thickness decision.
Modeled HBC power-conversion-efficiency design waterfall
Power-conversion efficiency (%)
26.5
27.0
27.5
28.0
28.5
28.75
Certified reference 26.74% · measured
27.123%
Modeled baselineKnown HBC stack replay
28.107%+0.984 pp
Published roadmapAt the original 175-µm thickness
28.513%+0.406 pp
28.457–28.573%
sensitivity
sensitivity
75-µm interventionPredeclared thickness decision
How this gets used in the field
Turn measurements from a working Si line into a smaller, sharper set of experiments for the next wafer run.
Engineering workflow
From a measured cell to the next decision.
Solar Device Studio is designed to sit between characterization and fabrication: it replays the device you have, exposes where performance is being lost, and tests physically declared changes before the team spends another process cycle.
1
Characterize the actual cell
Bring measured optical response, wafer thickness, base doping, lifetime, junction quality, contact resistance, and terminal J-V with source lineage.
2
Replay the production baseline
Check that the declared device state reproduces the known cell inside fixed Jsc, Voc, fill-factor, and PCE gates before exploring changes.
3
Compare candidate interventions
Test a thinner or thicker wafer, improved front optics, longer lifetime, a cleaner junction, or lower contact resistance as explicit scenarios.
4
Send one constrained experiment forward
Hand the lab a ranked design direction, the measurements that matter, the expected terminal response, and the uncertainty that remains.
Qualification boundary: this is decision support for declared device states inside the qualified Si Al-BSF architecture. It is not yet a blind process-recipe predictor, yield model, or production certification.
Designed for decisions
Where a materials platform becomes a device-engineering platform.
DESIGN
Compare candidate device states
Change thickness, optical quality, lifetime, doping, junction quality, or contact resistance and see the terminal consequence in one consistent calculation.
DIAGNOSE
Find which layer owns the loss
Separate optical, transport, recombination, junction, contact, and boundary contributions before committing laboratory time.
VALIDATE
Challenge known devices first
Replay published or laboratory device states, preserve failed rows, and test fixed gates before trusting a new design direction.
TRANSFER
Hand off measurable specifications
Turn the chosen state into explicit measurement requirements for optical response, doping, lifetime, junction quality, resistance, and terminal J-V.
EXPAND
Connect to the Materials engine
Use band gap, mobility, contacts, surfaces, and stack-level material choices from the wider FluxMateria platform as the design domain grows.
AUDIT
Know exactly what is claimed
Every result declares which inputs were measured, which values were calculated, which gates passed, and which external evidence is still missing.
Scope & limitations
The page is strongest when the boundary is explicit.
Validated now
- Conventional p-type crystalline-silicon cells with a full-area aluminium back-surface field.
- Parameterized device calculations using declared optical response, lifetime, doping, junction quality, and contact resistance.
- Terminal Jsc, Voc, fill factor, and PCE with fixed accuracy and robustness gates.
- Internal qualification plus one independent same-device published-profile check.
- No fitted correction factors and no outcome-selected boundary.
Pending next
- External laboratory qualification using instrument-native optical data, direct doping measurements, multiple cells, and multiple process lots.
- Blind prediction of an entirely new fabrication process from process recipe alone.
- Forward prediction of manufacturing-dependent lifetime and contact quality without declared device-state inputs.
- Independent qualification of PERC, TOPCon, heterojunction, tandem, and thin-film architectures.
- Production certification or warranty-grade yield prediction.
Planned expansion · not yet qualified
Today: one silicon architecture.
Destination: a multi-material device studio.
The present Si Al-BSF module is the first complete vertical slice. These are the next capability domains—each requiring its own physics closure, evidence panel, and qualification gates before public promotion.
01 / MATERIALS
Beyond crystalline silicon
Extend the same materials-to-device chain to germanium, carbon and diamond systems, III-V absorbers such as GaAs and InP, II-VI and chalcogenide absorbers, and emerging perovskite families.
02 / SILICON DEVICES
Advanced Si architectures
Add architecture-specific surface, passivation, contact, and transport treatment for PERC, TOPCon, heterojunction, interdigitated-back-contact, and other high-efficiency silicon cells.
03 / MULTIJUNCTION
Tandems and stacked absorbers
Compose optical sharing, current matching, interface losses, tunnel connections, and thermal operating state across silicon tandems and wider multi-junction stacks.
04 / PROCESS
Process-to-device prediction
Move upstream from declared device state toward fabrication-aware prediction: how deposition, diffusion, annealing, passivation, texturing, and metallization change the measurable state of the finished cell.
05 / MODULES
Cell-to-module engineering
Carry cell behavior into interconnects, encapsulation, mismatch, shading, bypass behavior, thermal coupling, packaging, and module-level power output.
06 / FIELD
Real operating environments
Add temperature cycles, spectral shifts, angle of incidence, irradiance variation, degradation, reliability, and uncertainty propagation toward field-energy and lifetime decisions.
07 / DISCOVERY
Inverse device design
Search material, layer, interface, and geometry combinations against explicit performance and manufacturability constraints, while preserving the evidence behind every candidate.
08 / QUALIFICATION
Laboratory-connected validation
Ingest instrument-native optical, lifetime, doping, J-V, and process metadata; run sealed predictions; compare across cells and lots; and generate reviewer-ready qualification packets.
09 / OPERATIONS
Yield and decision intelligence
Only after multi-lot evidence exists: connect physical variation to yield windows, process control, reliability risk, and manufacturing decisions without hiding uncertainty behind a single score.
The governing rule stays the same: a future capability is not labeled validated merely because it can run. Every new material, architecture, and operating domain must earn its own evidence and pass its own frozen gates.
Go deeper than the headline
Inspect the complete benchmark or follow the same-device Si Al-BSF story from source record to final decision.
Benchmark
Every gate, dataset boundary, and limitation.
See the 384-device internal qualification and the independent published-profile transfer check reported separately against the same frozen Jsc, Voc, fill-factor, and PCE goals.
4 / 4 terminal gates passed
Case study
Can the module improve a SOTA-class Si cell?
See the precedent-anchored 75-µm HBC intervention, the thickness-dependent optical penalty, the 28.51% research projection, and the exact experiment needed to test it.
26.74% certified → 28.51% simulated
Solar Device Studio
Bring a silicon device state.
Leave with a physics-backed decision.
Use FluxMateria to connect materials, device physics, terminal performance, and validation in one auditable workflow.