From 26.74% certified to 28.51% simulated.
FluxMateria took the complete published loss budget of a large-area silicon heterojunction back-contact cell, added one target-blind thin-wafer intervention, and produced a lab-testable design that clears a 5% modeled relative-gain gate.
Can the module propose a credible way past a state-of-the-art silicon design?
The published device state
A high-performance HBC cell with enough disclosed physics to support an auditable design experiment.
What the source already proposed
The paper's own roadmap reaches 27.7% by combining four experimentally motivated changes.
- Passivate the wafer edge and suppress rear electrical shading.
- Improve the front antireflection stack and rear reflector.
- Use lower-resistance nanocrystalline selective contacts.
- Strengthen field-effect and polarity-boundary passivation.
The FluxMateria intervention
One additional change, selected before terminal efficiency was calculated.
Freeze the primary-source loss budget
The article and official source-data archive fix the baseline geometry, optical losses, recombination terms, resistance, lifetime, resistivity interval, and terminal result. The current efficiency record is reporting context only; it does not select the design.
Identify the coupled constraint
A thinner wafer reduces the volume available for bulk recombination, but can lose long-wavelength current. The source's improved rear reflector creates a double-pass path that can compensate for the reduced physical thickness.
Select thickness without an efficiency target
An independent study has already certified a 74-µm thin silicon heterojunction cell. The rule was fixed in advance: round that demonstrated thickness to the nearest 5-µm pilot grid. The result is 75 µm. No PCE value enters that selection.
Calculate the optical penalty
The module computes the thickness-dependent double-pass absorption before terminal scoring, reducing roadmap Jsc from 42.8 to 42.65 mA/cm². Recombination terms and 0.12 ohm-cm² resistance remain at the published roadmap values.
Stress the reported wafer interval
The calculation is repeated at both published resistivity endpoints. The 5% relative-gain gate must survive the full retained interval, not only the midpoint.
The candidate crosses the design gate
Deterministic parameterized simulation under the declared source inputs.
| Device state | Jsc | Voc | Fill factor | PCE |
|---|---|---|---|---|
| Certified published full-area cell | 42.1 mA/cm² | 0.745 V | 0.8529 | 26.74% |
| FluxMateria baseline replay | 42.10 mA/cm² | 0.7724 V | 0.8340 | 27.123% |
| Published roadmap inputs, 175 µm | 42.80 mA/cm² | 0.7742 V | 0.8482 | 28.107% |
| FluxMateria candidate, 75 µm | 42.65 mA/cm² | 0.7873 V | 0.8492 | 28.513% |
Across the reported 1.2–1.5 ohm-cm resistivity interval, projected PCE is 28.46–28.57% and relative modeled gain remains 5.05–5.19%. The model's baseline replay is 0.383 percentage points above the certified cell and 27 mV high in Voc; that discrepancy is retained as evidence that HBC is not yet an externally qualified architecture.
What this case establishes
A genuine design output, with a deliberately hard claim boundary.
Supported by this case
- Solar Device Studio can turn a published SOTA-class loss budget into a concrete, process-addressable device proposal.
- The 75-µm thickness comes from an independent certified thin-SHJ precedent, not from searching against a desired efficiency.
- The module explicitly charges the thinner cell for its predicted optical-current loss before calculating the terminal result.
- The modeled gain is 5.13% relative to the model's own baseline and remains above 5% at both reported resistivity endpoints.
- The module adds 0.406 PCE percentage points beyond the same model at the paper's 175-µm roadmap state.
Not supported until a lab builds it
- This is not a measured 28.51% cell and not a new world record.
- The double-pass absorption calculation is not a full textured optical ray trace.
- The published roadmap's improved optics, contacts, and passivation must all be achieved together on a 75-µm HBC wafer.
- The 74-µm precedent is an SHJ device, not an HBC manufacturing-yield demonstration.
- HBC remains outside the currently qualified Al-BSF benchmark scope.
Build the three-arm HBC split-lot experiment.
The decisive next step is not another simulation iteration. Arm A reproduces the 175-µm baseline, Arm B applies the published roadmap at 175 µm, and Arm C applies the same roadmap at 75 µm. This separates the roadmap contribution from the thickness-only increment.
Trace the model, source data, and qualification boundary.
The case-study projection extends beyond the qualified Al-BSF benchmark and is labeled accordingly. The primary article and its official numerical source archive are linked directly.
Download the audit-ready case packet
The ZIP contains a plain-language PDF, machine-readable inputs and results, a public receipt, source lineage, limitations, checksums, and the exact three-arm validation request. It contains no proprietary equations, source code, or third-party spreadsheets.